1. Field of the Invention
The present invention relates to a method of manufacturing a silicon carbide semiconductor device.
2. Description of the Background Art
In manufacturing a semiconductor device, the step of selectively forming an impurity region in a semiconductor substrate is performed. For example, in manufacturing an n-channel type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), in order to obtain an npn structure, the step of partially forming a p-type impurity region in an n-type semiconductor substrate and further partially forming an n-type impurity region in this p-type impurity region is often performed. Namely, impurity regions different in extension from each other are formed. Both of the impurity regions should be formed in a self-aligned manner, in order to suppress variation in characteristics of the MOSFET, in particular, variation in channel length. In a case where a silicon substrate is employed as a semiconductor substrate, a double diffusion technique with which extension of an impurity region is adjusted by adjusting a degree of progress of impurity diffusion through heat treatment has widely been used.
In a case where a silicon carbide substrate is employed as a semiconductor substrate, however, a diffusion coefficient of an impurity is small and a region into which ions have been implanted becomes an impurity region substantially as it is through heat treatment. Therefore, it is difficult to employ the double diffusion technique. Thus, in order to obtain impurity regions formed in a self-aligned manner, a size of an opening in a mask for ion implantation should be adjusted. For example, according to Japanese Patent Laying-Open No. 2000-22137 (Patent Literature 1), a polycrystalline silicon film or an oxide film formed by oxidizing the same is employed as a mask and different impurity regions are formed by making use of movement of a mask end owing to oxidation or oxide film removal.
According to the technique described in the literature above, a sidewall of an opening is subjected to thermal oxidation in order to narrow the opening in a mask and the oxide film is removed in order to widen the opening narrowed as such. A thermal oxidation step for adjusting the opening in the mask, however, may often be undesirable or difficult. Specifically, a high temperature approximately from 900 to 1200° C. required in the thermal oxidation step may give rise to a problem. For example, in a case where a metal underlying layer is formed on a silicon carbide substrate, alloying may occur between a metal underlying film and the silicon carbide substrate at a high temperature. In addition, a rate of oxidation in the thermal oxidation step is not much high, and for example, a rate of steam oxidation is around 15 nm/minute. Therefore, efficiency in semiconductor device production may be low.
Then, the following method is available as a method of narrowing an opening in a mask. Initially, a film is formed on a silicon carbide substrate provided with a mask having an opening. As the film is formed on a sidewall of the opening, the opening is narrowed. Then, anisotropic etching allows a portion of the film on the sidewall to remain in the opening in the mask, while the remaining portion is removed. The opening narrowed by the film can thus be obtained. With this method, however, anisotropic etching should be stopped at appropriate timing. If etching is stopped too early, a portion of the film to be removed remains and the remaining portion may interfere ion implantation. If etching is stopped too late, the film does not sufficiently remain on the sidewall and the opening may not sufficiently be narrowed. Therefore, simply by performing this method, it is difficult to accurately form an impurity region.